Over the past twenty-five years or so, the primary challenge of very large scale integration (VLSI) has been the integration of an ever-increasing number of metal oxide semiconductor field effect transistor (MOSFET) devices with high yield and reliability. This was achieved mainly in the prior art by scaling down the MOSFET channel length without excessive short-channel effects. As is known to those skilled in the art, short-channel effects are the decrease in threshold voltage Vt in short-channel devices due to two-dimensional electrostatic charge sharing between the gate and the source/drain diffusions.
As the 45 nm node and the 32 nm node generations of complementary metal-oxide-semiconductor (CMOS) devices are approached, scaling of a transistor's gate length becomes imperative. However, the scaling effort is significantly limited by conventional lithographic printing, which has been used for patterning the gates of such transistors. The current 0.93 NA (numerical aperture) lithographic tool used in patterning the gates can only resolve 90 nm line width. Future 1.2 NA immersion lithographic tools are expected to print 70 nm line widths. As such, there is a need to reduce the gate length of transistors below 60, preferably below 50, nm.
Moreover, the line edge roughness and critical dimension variation of conventional lithography results in more significant Vt variation due to smaller feature size.
In view of the above, there is a need to provide a method of scaling semiconductor transistors to have sub-lithographic (less than 60, preferably less than about 50, nm) gate lengths.